Dr. Karthik Ganesan
Dr. Karthik Ganesan
Vmware Inc., PhD from University of Texas at Austin
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Synthesizing memory-level parallelism aware miniature clones for spec cpu2006 and implantbench workloads
K Ganesan, J Jo, LK John
2010 IEEE International Symposium on Performance Analysis of Systems …, 2010
Espnet-slu: Advancing spoken language understanding through espnet
S Arora, S Dalmia, P Denisov, X Chang, Y Ueda, Y Peng, Y Zhang, ...
ICASSP 2022-2022 IEEE International Conference on Acoustics, Speech and …, 2022
System-level max power (SYMPO) a systematic approach for escalating system-level power consumption using synthetic benchmarks
K Ganesan, J Jo, WL Bircher, D Kaseridis, Z Yu, LK John
Proceedings of the 19th international conference on Parallel architectures …, 2010
MAximum Multicore POwer (MAMPO) an automatic multithreaded synthetic power virus generation framework for multicore systems
K Ganesan, LK John
Proceedings of 2011 International Conference for High Performance Computing …, 2011
Next-generation performance counters: Towards monitoring over thousand concurrent events
V Salapura, K Ganesan, A Gara, M Gschwind, JC Sexton, RE Walkup
ISPASS 2008-IEEE International Symposium on Performance Analysis of Systems …, 2008
Automatic Generation of Miniaturized Synthetic Proxies for Target Applications to Efficiently Design Multicore Processors
K Ganesan, LK John
IEEE Transactions on Computers, 2013
The what's next intermittent computing architecture
K Ganesan, J San Miguel, NE Jerger
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
The eh model: Early design space exploration of intermittent processor architectures
J San Miguel, K Ganesan, M Badr, C Xia, R Li, H Hsiao, NE Jerger
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
Generation, validation and analysis of SPEC CPU2006 simulation points based on branch, memory and TLB characteristics
K Ganesan, D Panwar, LK John
Computer Performance Evaluation and Benchmarking: SPEC Benchmark Workshop …, 2009
The EH model: Analytical exploration of energy-harvesting architectures
J San Miguel, K Ganesan, M Badr, NE Jerger
IEEE Computer Architecture Letters 17 (1), 76-79, 2017
A performance counter based workload characterization on Blue Gene/P
K Ganesan, L John, V Salapura, J Sexton
2008 37th International Conference on Parallel Processing, 330-337, 2008
N-best ASR transformer: Enhancing SLU performance using multiple ASR hypotheses
K Ganesan, P Bamdev, A Venugopal, A Tushar
arXiv preprint arXiv:2106.06519, 2021
Clinical application of a novel next generation sequencing assay for CYP21A2 gene in 310 cases of 21- hydroxylase congenital adrenal hyperplasia from India
P Gangodkar, V Khadilkar, P Raghupathy, R Kumar, AA Dayal, D Dayal, ...
Endocrine 71, 189-198, 2021
A study on the integration of pre-trained ssl, asr, lm and slu models for spoken language understanding
Y Peng, S Arora, Y Higuchi, Y Ueda, S Kumar, K Ganesan, S Dalmia, ...
2022 IEEE Spoken Language Technology Workshop (SLT), 406-413, 2023
Methods to utilize heterogeneous memories with variable properties
L John, JH Ryoo, HM Hsu, K Ganesan
US Patent App. 15/853,665, 2018
On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system
N Venkateswaran, VK Elangovan, K Ganesan, TPRS Sagar, ...
2008 IEEE International Symposium on Parallel and Distributed Processing, 1-8, 2008
i-mirror: A software managed die-stacked dram-based memory subsystem
JH Ryoo, K Ganesan, YM Chen, LK John
2015 27th International Symposium on Computer Architecture and High …, 2015
Altocumulus: Scalable scheduling for nanosecond-scale remote procedure calls
J Zhao, I Uwizeyimana, K Ganesan, MC Jeffrey, NE Jerger
2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 423-440, 2022
Findadaptnet: Find and insert adapters by learned layer importance
J Huang, K Ganesan, S Maiti, YM Kim, X Chang, P Liang, S Watanabe
ICASSP 2023-2023 IEEE International Conference on Acoustics, Speech and …, 2023
Low latency, high bandwidth memory subsystem incorporating die-stacked DRAM
JH Ryoo, K Ganesan, YM Chen
US Patent 9,406,361, 2016
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