| Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ... 2017 symposium on VLSI technology, T230-T231, 2017 | 877 | 2017 |
| Recessed metal liner contact with copper fill P Adusumilli, VS Basker, H Bu, Z Liu US Patent 9,496,225, 2016 | 331 | 2016 |
| A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 189 | 2016 |
| High-k metal gate fundamental learning and multi-Vt options for stacked nanosheet gate-all-around transistor J Zhang, T Ando, CW Yeung, M Wang, O Kwon, R Galatage, R Chao, ... 2017 IEEE International Electron Devices Meeting (IEDM), 22.1. 1-22.1. 4, 2017 | 62 | 2017 |
| Air spacer for 10nm FinFET CMOS and beyond K Cheng, C Park, C Yeung, S Nguyen, J Zhang, X Miao, M Wang, ... 2016 IEEE International Electron Devices Meeting (IEDM), 17.1. 1-17.1. 4, 2016 | 55 | 2016 |
| Sub- -cm2 n-Type Contact Resistivity for FinFET Technology H Niimi, Z Liu, O Gluschenkov, S Mochizuki, J Fronheiser, J Li, ... IEEE Electron Device Letters 37 (11), 1371-1374, 2016 | 55 | 2016 |
| Forming wrap-around silicide contact on finFET D Guo, H Jagannathan, Z Liu, S Mochizuki US Patent 9,318,581, 2016 | 55 | 2016 |
| Parasitic resistance reduction strategies for advanced CMOS FinFETs beyond 7nm H Wu, O Gluschenkov, G Tsutsui, C Niu, K Brew, C Durfee, C Prindle, ... 2018 IEEE International Electron Devices Meeting (IEDM), 35.4. 1-35.4. 4, 2018 | 45 | 2018 |
| Mn-doped AlN nanowires with room temperature ferromagnetic ordering Y Yang, Q Zhao, XZ Zhang, ZG Liu, CX Zou, B Shen, DP Yu Applied Physics Letters 90 (9), 2007 | 45 | 2007 |
| FinFET performance with Si: P and Ge: Group-III-Metal metastable contact trench alloys O Gluschenkov, Z Liu, H Niimi, S Mochizuki, J Fronheiser, X Miao, J Li, ... 2016 IEEE International Electron Devices Meeting (IEDM), 17.2. 1-17.2. 4, 2016 | 42 | 2016 |
| Independent gate vertical FinFET structure VS Basker, Z Liu, T Yamashita, CC Yeh US Patent 9,190,466, 2015 | 38 | 2015 |
| Low resistance source drain contact formation O Gluschenkov, Z Liu, S Mochizuki, H Niimi, CC Yeh US Patent 9,972,682, 2018 | 37 | 2018 |
| A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs T Yamashita, S Mehta, VS Basker, R Southwick, A Kumar, ... 2015 Symposium on VLSI Technology, 154-155, 2015 | 33 | 2015 |
| Punch through stopper in bulk finFET device VS Basker, Z Liu, T Yamashita, CC Yeh US Patent 9,559,191, 2017 | 32 | 2017 |
| Ti and NiPt/Ti liner silicide contacts for advanced technologies P Adusumilli, E Alptekin, M Raymond, N Breil, F Chafik, C Lavoie, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 29 | 2016 |
| Finfet including improved epitaxial topology VS Basker, Z Liu, T Yamashita, CC Yeh US Patent 9,257,537, 2016 | 25 | 2016 |
| Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap K Cheng, Z Liu, S Naczas, H Wu, P Xu US Patent 10,056,289, 2018 | 24 | 2018 |
| Inelastic electron tunneling spectroscopy study of thin gate dielectrics JW Reiner, S Cui, Z Liu, M Wang, CH Ahn, TP Ma Advanced Materials 22 (26‐27), 2962-2968, 2010 | 24 | 2010 |
| Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices H Wu, K Cheng, J Wang, Z Liu US Patent 10,566,246, 2020 | 23 | 2020 |
| Forming wrap-around silicide contact on finFET D Guo, H Jagannathan, Z Liu, S Mochizuki US Patent 9,397,197, 2016 | 22 | 2016 |
Praneet AdusumilliIBM ResearchVerified email at us.ibm.com
