| Advances, challenges and opportunities in 3D CMOS sequential integration P Batude, M Vinet, B Previtali, C Tabone, C Xu, J Mazurier, O Weber, ... 2011 International Electron Devices Meeting, 7.3. 1-7.3. 4, 2011 | 408 | 2011 |
| Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance F Mayer, C Le Royer, JF Damlencourt, K Romanjek, F Andrieu, C Tabone, ... 2008 IEEE International Electron Devices Meeting, 1-5, 2008 | 372 | 2008 |
| Planar Fully depleted SOI technology: A Powerful architecture for the 20nm node and beyond O Faynot, F Andrieu, O Weber, C Fenouillet-Béranger, P Perreau, ... 2010 International Electron Devices Meeting, 3.2. 1-3.2. 4, 2010 | 323 | 2010 |
| Engineered substrates for future More Moore and More than Moore integrated devices L Clavelier, C Deguet, L Di Cioccio, E Augendre, A Brugere, P Gueguen, ... 2010 International Electron Devices Meeting, 2.6. 1-2.6. 4, 2010 | 273 | 2010 |
| Novel integration process and performances analysis of Low STandby Power (LSTP) 3D Multi-Channel CMOSFET (MCFET) on SOI with Metal/High-K Gate stack E Bernard, T Ernst, B Guillaumot, N Vulliet, V Barral, V Maffini-Alvaro, ... 2008 Symposium on VLSI Technology, 16-17, 2008 | 254 | 2008 |
| Multi-UTBB FDSOI Device Architectures for Low-Power CMOS Circuit JP Noel, O Thomas, MA Jaud, O Weber, T Poiroux, C Fenouillet-Beranger, ... IEEE Transactions on Electron Devices 58 (8), 2473-2482, 2011 | 235 | 2011 |
| High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding O Weber, O Faynot, F Andrieu, C Buj-Dufournet, F Allain, P Scheiblin, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 206 | 2008 |
| Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters M Cassé, L Thevenod, B Guillaumot, L Tosti, F Martin, J Mitard, O Weber, ... IEEE Transactions on Electron Devices 53 (4), 759-768, 2006 | 193 | 2006 |
| Improved split CV method for effective mobility extraction in sub-0.1-μm Si MOSFETs K Romanjek, F Andrieu, T Ernst, G Ghibaudo IEEE Electron Device Letters 25 (8), 583-585, 2004 | 188 | 2004 |
| FDSOI devices with thin BOX and ground plane integration for 32 nm node and below C Fenouillet-Beranger, S Denorme, P Perreau, C Buj, O Faynot, F Andrieu, ... Solid-State Electronics 53 (7), 730-734, 2009 | 164 | 2009 |
| Engineering strained silicon on insulator wafers with the Smart CutTM technology B Ghyselen, JM Hartmann, T Ernst, C Aulnette, B Osternaud, ... Solid-state electronics 48 (8), 1285-1296, 2004 | 160 | 2004 |
| Performance and design considerations for gate-all-around stacked-NanoWires FETs S Barraud, V Lapras, B Previtali, MP Samson, J Lacord, S Martinie, ... 2017 IEEE international electron devices meeting (IEDM), 29.2. 1-29.2. 4, 2017 | 146 | 2017 |
| 14nm FDSOI technology for high speed and energy efficient applications O Weber, E Josse, F Andrieu, A Cros, E Richard, P Perreau, E Baylac, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 117 | 2014 |
| Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond F Andrieu, O Weber, J Mazurier, O Thomas, JP Noel, ... 2010 Symposium on VLSI Technology, 57-58, 2010 | 116 | 2010 |
| Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below C Fenouillet-Beranger, P Perreau, S Denorme, L Tosti, F Andrieu, ... 2009 Proceedings of the European Solid State Device Research Conference, 89-92, 2009 | 104 | 2009 |
| Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2gate stack V Barral, T Poiroux, F Andrieu, C Buj-Dufournet, O Faynot, T Ernst, ... 2007 IEEE International Electron Devices Meeting, 61-64, 2007 | 100 | 2007 |
| Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack T Ernst, C Dupre, C Isheden, E Bernard, R Ritzenthaler, V Maffini-Alvaro, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 97 | 2006 |
| 7-levels-stacked nanosheet GAA transistors for high performance computing S Barraud, B Previtali, C Vizioz, JM Hartmann, J Sturm, J Lassarre, ... 2020 IEEE symposium on VLSI technology, 1-2, 2020 | 93 | 2020 |
| Nanoscaled MOSFET Transistors on Strained Si, SiGe, Ge Layers: Some Integration and Electrical Properties Features TP Ernst, F Andrieu, O Weber, JM Hartmann, C Dupre, O Faynot, ... ECS Transactions 3 (7), 947, 2006 | 90 | 2006 |
| 3D Sequential Integration: Application-driven technological achievements and guidelines P Batude, L Brunet, C Fenouillet-Beranger, F Andrieu, JP Colinge, ... 2017 IEEE International Electron Devices Meeting (IEDM), 3.1. 1-3.1. 4, 2017 | 89 | 2017 |
