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Andrea Bonetti
Andrea Bonetti
Sony AI
Dirección de correo verificada de sony.com
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Polarbear: A 28-nm FD-SOI ASIC for decoding of polar codes
P Giard, A Balatsoukas-Stimming, TC Müller, A Bonetti, C Thibeault, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 7 (4 …, 2017
602017
An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop
A Bonetti, A Teman, A Burg
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1850-1853, 2015
292015
Multipliers-driven perturbation of coefficients for low-power operation in reconfigurable FIR filters
A Bonetti, A Teman, P Flatresse, A Burg
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2388-2400, 2017
272017
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment
J Constantin, A Bonetti, A Teman, C Müller, L Schmid, A Burg
European Solid-State Circuits Conference, ESSCIRC Conference 2016: 42nd, 261-264, 2016
252016
Impact of memory voltage scaling on accuracy and resilience of deep learning based edge devices
BW Denkinger, F Ponzina, SS Basu, A Bonetti, S Balási, M Ruggiero, ...
IEEE Design & Test 37 (2), 84-92, 2019
162019
Current-based data-retention-time characterization of gain-cell embedded DRAMs across the design and variations space
R Giterman, A Bonetti, EV Bravo, T Noy, A Teman, A Burg
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (4), 1207-1217, 2020
112020
A 24 kb single-well mixed 3T gain-cell eDRAM with body-bias in 28 nm FD-SOI for refresh-free DSP applications
J Narinx, R Giterman, A Bonetti, N Frigerio, C Aprile, A Burg, Y Leblebici
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 219-222, 2019
112019
FPGA-based emulation of embedded DRAMs for statistical error resilience evaluation of approximate computing systems
M Widmer, A Bonetti, A Burg
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
112019
Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder
P Meinerzhagen, A Bonetti, G Karakonstantis, C Roth, F Giirkaynak, ...
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1426-1429, 2015
112015
A tool for the assisted design of charge redistribution SAR ADCs
S Brenna, A Bonetti, A Bonfanti, AL Lacaita
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
102015
GC-eDRAM with body-bias compensated readout and error detection in 28-nm FD-SOI
R Giterman, A Bonetti, A Burg, A Teman
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (12), 2042-2046, 2019
92019
A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs
S Brenna, A Bonetti, A Bonfanti, AL Lacaita
2014 37th International Convention on Information and Communication …, 2014
92014
An efficient tool for the assisted design of SAR ADCs capacitive DACs
S Brenna, A Bonetti, A Bonfanti, AL Lacaita
Integration 53, 88-99, 2016
82016
Standardisation Challenges for Digital Inputs and Outputs of Protection Functions in IEC 60255 series
V LEITLOFF, H CHEN, D CHEN, A BONETTI, L XU, A MOHAMED
8*
Gain-cell embedded DRAMs: Modeling and design space
A Bonetti, R Golman, R Giterman, A Teman, A Burg
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (3), 646-659, 2020
72020
Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters
S Brenna, L Bettini, A Bonetti, A Bonfanti, AL Lacaita
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP …, 2015
62015
Low power and compact successive approximation ADC for bioelectronic chips
A BONETTI
Italy, 2012
62012
A construction kit for efficient low power neural network accelerator designs
P Jokic, E Azarkhish, A Bonetti, M Pons, S Emery, L Benini
ACM Transactions on Embedded Computing Systems (TECS) 21 (5), 1-36, 2022
52022
Data-retention-time characterization of gain-cell eDRAMs across the design and variations space
EV Bravo, A Bonetti, A Burg
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019
42019
Automated integration of dual-edge clocking for low-power operation in nanometer nodes
A Bonetti, N Preyss, A Teman, A Burg
ACM Transactions on Design Automation of Electronic Systems (TODAES) 22 (4 …, 2017
42017
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