Kewal Saluja
Kewal Saluja
Professor of Electrical and Computer Engineering, University of Wisconsin - Madison
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Sensor deployment strategy for target detection
T Clouqueur, V Phipatanasuphorn, P Ramanathan, KK Saluja
Proceedings of the 1st ACM international workshop on Wireless sensor …, 2002
A tutorial on built-in self-test. I. Principles
VD Agrawal, CR Kime, KK Saluja
IEEE Design & Test of Computers 10 (1), 73-82, 1993
Scheduling tests for VLSI systems under power constraints
RM Chou, KK Saluja, VD Agrawal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5 (2), 175-185, 1997
Fault tolerance in collaborative sensor networks for target detection
T Clouqueur, KK Saluja, P Ramanathan
IEEE transactions on computers 53 (3), 320-333, 2004
On low-capture-power test generation for scan testing
X Wen, Y Yamashita, S Kajihara, LT Wang, KK Saluja, K Kinoshita
23rd IEEE VLSI Test Symposium (VTS'05), 265-270, 2005
Sensor deployment strategy for detection of targets traversing a region
T Clouqueur, V Phipatanasuphorn, P Ramanathan, KK Saluja
Mobile networks and applications 8, 453-461, 2003
Low-capture-power test generation for scan-based at-speed testing
X Wen, Y Yamashita, S Morishima, S Kajihara, LT Wang, KK Saluja, ...
IEEE International Conference on Test, 2005., 10 pp.-1028, 2005
Testing computer hardware through data compression in space and time
KK Saluja
Proc. ITC, 1983, 83-88, 1983
Test scheduling and control for VLSI built-in self-test
GL Craig, CR Kine, KK Saluja
IEEE transactions on Computers 37 (9), 1099-1109, 1988
An efficient algorithm for sequential circuit test generation
TP Kelsey, KK Saluja, SY Lee
IEEE Transactions on Computers 42 (11), 1361-1371, 1993
A new ATPG method for efficient capture power reduction during scan testing
X Wen, S Kajihara, K Miyase, T Suzuki, KK Saluja, LT Wang, ...
24th IEEE VLSI Test Symposium, 6 pp.-65, 2006
A concurrent testing technique for digital circuits
KK Saluja, R Sharma, CR Kime
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1988
Fault detecting test sets for Reed-Muller canonic networks
KK Saluja, SM Reddy
IEEE transactions on computers 100 (10), 995-998, 1975
Power constraint scheduling of tests
RM Chou, KK Saluja, VD Agrawal
Proceedings of 7th International Conference on VLSI Design, 271-274, 1994
A study of time-redundant fault tolerance techniques for high-performance pipelined computers
GS Sohi, M Franklin, KK Saluja
[1989] The Nineteenth International Symposium on Fault-Tolerant Computing …, 1989
Incorporating testability considerations in high-level synthesis
A Mujumdar, R Jain, K Saluja
Journal of Electronic Testing 5, 43-55, 1994
A data compression technique for built-in self-test
SM Reddy, KK Saluja, MG Karpovsky
IEEE transactions on computers 37 (9), 1151-1156, 1988
A yield improvement methodology using pre-and post-silicon statistical clock scheduling
JL Tsai, DH Baik, CCP Chen, KK Saluja
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004
Value-fusion versus decision-fusion for fault-tolerance in collaborative target detection in sensor networks
T Clouqueur, P Ramanathan, KK Saluja, KC Wang
Proceedings of Fourth International Conference on Information Fusion, 1-7, 2001
Test application time reduction for sequential circuits with scan
SY Lee, KK Saluja
IEEE transactions on computer-aided design of integrated circuits and …, 1995
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