D. Fey
D. Fey
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Cited by
Cited by
Hpx: A task based programming model in a global address space
H Kaiser, T Heller, B Adelstein-Lelbach, A Serio, D Fey
Proceedings of the 8th International Conference on Partitioned Global …, 2014
High performance stencil code algorithms for GPGPUs
A Schäfer, D Fey
Procedia Computer Science 4, 2027-2036, 2011
Continuous integration and automation for DevOps
A Schaefer, M Reichenbach, D Fey
IAENG Transactions on Engineering Technologies: Special Edition of the World …, 2013
Optical interconnects for neural and reconfigurable VLSI architectures
D Fey, W Erhard, M Gruber, J Jahns, H Bartelt, G Grimm, L Hoppe, ...
Proceedings of the IEEE 88 (6), 838-848, 2000
A modeling methodology for resistive ram based on stanford-pku model with extended multilevel capability
J Reuben, D Fey, C Wenger
IEEE transactions on nanotechnology 18, 647-656, 2019
Libgeodecomp: A grid-enabled library for geometric decomposition codes
A Schäfer, D Fey
Recent Advances in Parallel Virtual Machine and Message Passing Interface …, 2008
Higher-level parallelization for local and distributed asynchronous task-based programming
H Kaiser, T Heller, D Bourgeois, D Fey
Proceedings of the First International Workshop on Extreme Scale Programming …, 2015
Performance investigations of genetic algorithms on graphics cards
J Hofmann, S Limmer, D Fey
Swarm and Evolutionary Computation 12, 33-47, 2013
Memristive devices for computing: Beyond CMOS and beyond von Neumann
HA Du Nguyen, J Yu, L Xie, M Taouil, S Hamdioui, D Fey
2017 IFIP/IEEE International Conference on Very Large Scale Integration …, 2017
Using HPX and LibGeoDecomp for scaling HPC applications on heterogeneous supercomputers
T Heller, H Kaiser, A Schäfer, D Fey
Proceedings of the Workshop on Latest Advances in Scalable Algorithms for …, 2013
A generic VHDL template for 2D stencil code applications on FPGAs
M Schmidt, M Reichenbach, D Fey
2012 IEEE 15th International Symposium on Object/Component/Service-Oriented …, 2012
Closing the performance gap with modern c++
T Heller, H Kaiser, P Diehl, D Fey, MA Schweitzer
High Performance Computing: ISC High Performance 2016 International …, 2016
Marching-pixels: a new organic computing paradigm for smart sensor processor arrays
D Fey, D Schmidt
Proceedings of the 2nd conference on Computing frontiers, 1-9, 2005
An analysis of core-and chip-level architectural features in four generations of intel server processors
J Hofmann, G Hager, G Wellein, D Fey
High Performance Computing: 32nd International Conference, ISC High …, 2017
Incorporating variability of resistive RAM in circuit simulations using the Stanford–PKU model
J Reuben, M Biglari, D Fey
IEEE Transactions on Nanotechnology 19, 508-518, 2020
Using the multi-bit feature of memristors for register files in signed-digit arithmetic units
D Fey
Semiconductor Science and Technology 29 (10), 104008, 2014
System architecture for network-attached FPGAs in the cloud using partial reconfiguration
B Ringlein, F Abel, A Ditter, B Weiss, C Hagleitner, D Fey
2019 29th International Conference on Field Programmable Logic and …, 2019
Execution-cache-memory performance model: Introduction and validation
J Hofmann, J Eitzinger, D Fey
arXiv preprint arXiv:1509.03118, 2015
Comparison of evolving uniform, non-uniform cellular automaton, and genetic programming for centroid detection with hardware agents
M Komann, A Mainka, D Fey
Parallel Computing Technologies: 9th International Conference, PaCT 2007 …, 2007
Analysis of intel’s haswell microarchitecture using the ecm model and microbenchmarks
J Hofmann, D Fey, J Eitzinger, G Hager, G Wellein
Architecture of Computing Systems–ARCS 2016: 29th International Conference …, 2016
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