| A CMOS silicon spin qubit R Maurand, X Jehl, D Kotekar-Patil, A Corna, H Bohuslavskyi, R Laviéville, ... Nature communications 7 (1), 13575, 2016 | 648 | 2016 |
| Planar Fully depleted SOI technology: A Powerful architecture for the 20nm node and beyond O Faynot, F Andrieu, O Weber, C Fenouillet-Béranger, P Perreau, ... 2010 International Electron Devices Meeting, 3.2. 1-3.2. 4, 2010 | 323 | 2010 |
| Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm S Barraud, M Berthome, R Coquand, M Cassé, T Ernst, MP Samson, ... IEEE Electron Device Letters 33 (9), 1225-1227, 2012 | 263 | 2012 |
| Probing the limits of gate-based charge sensing MF Gonzalez-Zalba, S Barraud, AJ Ferguson, AC Betz Nature communications 6 (1), 1-8, 2015 | 193 | 2015 |
| Performance of omega-shaped-gate silicon nanowire MOSFET with diameter down to 8 nm S Barraud, R Coquand, M Casse, M Koyama, JM Hartmann, ... IEEE Electron Device Letters 33 (11), 1526-1528, 2012 | 170 | 2012 |
| Gate-based high fidelity spin readout in a CMOS device M Urdampilleta, DJ Niegemann, E Chanrion, B Jadot, C Spence, ... Nature nanotechnology 14 (8), 737-741, 2019 | 151 | 2019 |
| Performance and design considerations for gate-all-around stacked-NanoWires FETs S Barraud, V Lapras, B Previtali, MP Samson, J Lacord, S Martinie, ... 2017 IEEE international electron devices meeting (IEDM), 29.2. 1-29.2. 4, 2017 | 147 | 2017 |
| Electrical Spin Driving by -Matrix Modulation in Spin-Orbit Qubits A Crippa, R Maurand, L Bourdet, D Kotekar-Patil, A Amisse, X Jehl, ... Physical review letters 120 (13), 137702, 2018 | 146 | 2018 |
| Cryogenic subthreshold swing saturation in FD-SOI MOSFETs described with band broadening H Bohuslavskyi, AGM Jansen, S Barraud, V Barral, M Cassé, L Le Guevel, ... IEEE Electron Device Letters 40 (5), 784-787, 2019 | 133 | 2019 |
| Revisited parameter extraction methodology for electrical characterization of junctionless transistors DY Jeon, SJ Park, M Mouis, M Berthomé, S Barraud, GT Kim, G Ghibaudo Solid-State Electronics 90, 86-93, 2013 | 124 | 2013 |
| Vertically stacked-nanowires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain S Barraud, V Lapras, MP Samson, L Gaben, L Grenouillet, ... 2016 IEEE International Electron Devices Meeting (IEDM), 17.6. 1-17.6. 4, 2016 | 122 | 2016 |
| Few-electron edge-state quantum dots in a silicon nanowire field-effect transistor B Voisin, VH Nguyen, J Renard, X Jehl, S Barraud, F Triozon, M Vinet, ... Nano letters 14 (4), 2094-2098, 2014 | 121 | 2014 |
| Electrical Control of g-Factor in a Few-Hole Silicon Nanowire MOSFET B Voisin, R Maurand, S Barraud, M Vinet, X Jehl, M Sanquer, J Renard, ... Nano letters 16 (1), 88-92, 2016 | 116 | 2016 |
| Electrically driven electron spin resonance mediated by spin–valley–orbit coupling in a silicon quantum dot A Corna, L Bourdet, R Maurand, A Crippa, D Kotekar-Patil, ... npj quantum information 4 (1), 6, 2018 | 111 | 2018 |
| Strain-induced performance enhancement of trigate and omega-gate nanowire FETs scaled down to 10-nm width R Coquand, M Casse, S Barraud, D Cooper, V Maffini-Alvaro, ... IEEE transactions on electron devices 60 (2), 727-732, 2012 | 103 | 2012 |
| 7-levels-stacked nanosheet GAA transistors for high performance computing S Barraud, B Previtali, C Vizioz, JM Hartmann, J Sturm, J Lassarre, ... 2020 IEEE symposium on VLSI technology, 1-2, 2020 | 93 | 2020 |
| Nanoscaled MOSFET Transistors on Strained Si, SiGe, Ge Layers: Some Integration and Electrical Properties Features TP Ernst, F Andrieu, O Weber, JM Hartmann, C Dupre, O Faynot, ... ECS Transactions 3 (7), 947, 2006 | 90 | 2006 |
| 3D Sequential Integration: Application-driven technological achievements and guidelines P Batude, L Brunet, C Fenouillet-Beranger, F Andrieu, JP Colinge, ... 2017 IEEE International Electron Devices Meeting (IEDM), 3.1. 1-3.1. 4, 2017 | 89 | 2017 |
| Low-temperature electrical characterization of junctionless transistors DY Jeon, SJ Park, M Mouis, S Barraud, GT Kim, G Ghibaudo Solid-State Electronics 80, 135-141, 2013 | 89 | 2013 |
| Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width R Coquand, S Barraud, M Cassé, P Leroux, C Vizioz, C Comboroure, ... Solid-State Electronics 88, 32-36, 2013 | 87 | 2013 |
