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Ramiro Taco
Ramiro Taco
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Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI
R Taco, I Levi, M Lanuzza, A Fish
Solid-State Electronics 117, 185-192, 2016
512016
An 88-fJ/40-MHz [0.4 V]–0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI
R Taco, I Levi, M Lanuzza, A Fish
IEEE Journal of Solid-State Circuits 54 (2), 560-568, 2018
362018
Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design
R Taco, I Levi, A Fish, M Lanuzza
2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel …, 2014
252014
A 0.8-V, 1.54-pJ/940-MHz dual-mode logic-based 16× 16-b booth multiplier in 16-nm FinFET
N Shavit, I Stanger, R Taco, M Lanuzza, A Fish
IEEE Solid-State Circuits Letters 3, 314-317, 2020
212020
Reconfigurable CMOS/STT-MTJ non-volatile circuit for logic-in-memory applications
E Garzón, B Zambrano, T Moposita, R Taco, LM Prócel, L Trojman
2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2020
192020
Ultralow voltage finFET-versus TFET-based STT-MRAM cells for IoT applications
E Garzón, M Lanuzza, R Taco, S Strangio
Electronics 10 (15), 1756, 2021
182021
Evaluation of dual mode logic in 28nm FD-SOI technology
R Taco, I Levi, M Lanuzza, A Fish
2017 IEEE international symposium on circuits and systems (ISCAS), 1-4, 2017
162017
Dynamic gate-level body biasing for subthreshold digital design
M Lanuzza, R Taco, D Albano
2014 IEEE 5th Latin American Symposium on Circuits and Systems, 1-4, 2014
162014
XNOR-bitcount operation exploiting computing-in-memory with STT-MRAMs
A Musello, E Garzón, M Lanuzza, LM Prócel, R Taco
IEEE Transactions on Circuits and Systems II: Express Briefs 70 (3), 1259-1263, 2023
132023
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology
R Taco, I Levi, M Lanuzza, A Fish
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 41-44, 2016
122016
Silicon evaluation of multimode dual mode logic for PVT-aware datapaths
I Stanger, N Shavit, R Taco, M Lanuzza, A Fish
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (9), 1639-1643, 2020
112020
Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines
D Albano, M Lanuzza, R Taco, F Crupi
International Journal of Circuit Theory and Applications 43 (11), 1523-1540, 2015
112015
Ultra‐Low‐Voltage Self‐Body Biasing Scheme and Its Application to Basic Arithmetic Circuits
R Taco, M Lanuzza, D Albano
VLSI Design 2015 (1), 540482, 2015
112015
Dual mode logic address decoder
L Yavits, R Taco, N Shavit, I Stanger, A Fish
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
102020
Energy efficient self-adaptive Dual Mode Logic address decoder
K Vicuña, C Mosquera, A Musello, S Benedictis, M Rendón, E Garzón, ...
Electronics 10 (9), 1052, 2021
72021
Robust dual mode pass logic (DMPL) for energy efficiency and high performance
I Stanger, N Shavit, R Taco, L Yavits, M Lanuzza, A Fish
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
62020
Efficiency of dual mode logic in nanoscale technology nodes
N Shavit, R Taco, A Fish
2018 IEEE International Conference on the Science of Electrical Engineering …, 2018
62018
A method for mitigation of droop timing errors including a 500 MHz droop detector and dual mode logic
Y Shifman, I Stanger, N Shavit, R Taco, A Fish, J Shor
IEEE Journal of Solid-State Circuits 57 (2), 596-608, 2021
52021
Process variation-aware datapath employing dual mode logic
N Shavit, I Stanger, R Taco, A Fish
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018
52018
DMTJ-based non-volatile ternary content addressable memory for energy-efficient high-performance systems
K Vicuña, LM Prócel, L Trojman, R Taco
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS), 1-4, 2022
42022
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