| Robust surface-potential-based compact model for GaN HEMT IC design S Khandelwal, C Yadav, S Agnihotri, YS Chauhan, A Curutchet, T Zimmer, ... IEEE Transactions on Electron Devices 60 (10), 3216-3222, 2013 | 136 | 2013 |
| Compact modeling of transition metal dichalcogenide based thin body transistors and circuit validation C Yadav, A Agarwal, YS Chauhan IEEE transactions on electron devices 64 (3), 1261-1268, 2017 | 57 | 2017 |
| Comparison of on-wafer TRL calibration to ISS SOLT calibration with open-short de-embedding up to 500 GHz S Fregonese, M Deng, M De Matos, C Yadav, S Joly, B Plano, C Raya, ... IEEE Transactions on Terahertz Science and Technology 9 (1), 89-97, 2018 | 53 | 2018 |
| Modeling of GaN-based normally-off FinFET C Yadav, P Kushwaha, S Khandelwal, JP Duarte, YS Chauhan, C Hu IEEE electron device letters 35 (6), 612-614, 2014 | 50 | 2014 |
| BSIM compact MOSFET models for SPICE simulation YS Chauhan, S Venugopalan, N Paydavosi, P Kushwaha, S Jandhyala, ... Proceedings of the 20th International Conference Mixed Design of Integrated …, 2013 | 39 | 2013 |
| Modeling the impact of substrate depletion in FDSOI MOSFETs P Kushwaha, N Paydavosi, S Khandelwal, C Yadav, H Agarwal, ... Solid-State Electronics 104, 6-11, 2015 | 33 | 2015 |
| Importance and requirement of frequency band specific RF probes EM models in sub-THz and THz measurements up to 500 GHz C Yadav, M Deng, S Fregonese, M Cabbia, M De Matos, B Plano, ... IEEE Transactions on Terahertz Science and Technology 10 (5), 558-563, 2020 | 29 | 2020 |
| Capacitance modeling in III–V FinFETs C Yadav, JP Duarte, S Khandelwal, A Agarwal, C Hu, YS Chauhan IEEE Transactions on Electron Devices 62 (11), 3892-3897, 2015 | 29 | 2015 |
| Charge-based modeling of transition metal dichalcogenide transistors including ambipolar, trapping, and negative capacitance effects C Yadav, P Rastogi, T Zimmer, YS Chauhan IEEE Transactions on Electron Devices 65 (10), 4202-4208, 2018 | 26 | 2018 |
| Analytical modeling and experimental validation of threshold voltage in BSIM6 MOSFET model H Agarwal, C Gupta, P Kushwaha, C Yadav, JP Duarte, S Khandelwal, ... IEEE journal of the Electron Devices Society 3 (3), 240-243, 2015 | 24 | 2015 |
| Analysis of high-frequency measurement of transistors along with electromagnetic and SPICE cosimulation S Fregonese, M Cabbia, C Yadav, M Deng, SR Panda, M De Matos, ... IEEE Transactions on Electron Devices 67 (11), 4770-4776, 2020 | 18 | 2020 |
| Surface potential based modeling of charge, current, and capacitances in DGTFET including mobile channel charge and ambipolar behaviour P Jain, C Yadav, A Agarwal, YS Chauhan Solid-State Electronics 134, 74-81, 2017 | 16 | 2017 |
| Compact modeling of charge, capacitance, and drain current in III–V channel double gate FETs C Yadav, M Agrawal, A Agarwal, YS Chauhan IEEE Transactions on Nanotechnology 16 (2), 347-354, 2017 | 16 | 2017 |
| Impact of on-Silicon de-embedding test structures and RF probes design in the Sub-THz range C Yadav, M Deng, S Fregonese, M DeMatos, B Plano, T Zimmer 2018 48th European Microwave Conference (EuMC), 21-24, 2018 | 15 | 2018 |
| Silicon test structures design for sub-THz and THz measurements M Cabbia, C Yadav, M Deng, S Fregonese, M De Matos, T Zimmer IEEE Transactions on Electron Devices 67 (12), 5639-5645, 2020 | 14 | 2020 |
| Band-to-band tunneling in Γ valley for Ge source lateral tunnel field effect transistor: thickness scaling P Jain, P Rastogi, C Yadav, A Agarwal, YS Chauhan Journal of Applied Physics 122 (1), 2017 | 14 | 2017 |
| Modeling of charge and quantum capacitance in low effective mass III-V FinFETs MD Ganeriwala, C Yadav, NR Mohapatra, S Khandelwal, C Hu, ... IEEE Journal of the Electron Devices Society 4 (6), 396-401, 2016 | 14 | 2016 |
| A comprehensive physics-based current–voltage SPICE compact model for 2-D-material-based top-contact bottom-gated Schottky-barrier FETs SA Ahsan, SK Singh, C Yadav, EG Marin, A Kloes, M Schwarz IEEE Transactions on Electron Devices 67 (11), 5188-5195, 2020 | 13 | 2020 |
| Modeling of quantum confinement and capacitance in III–V gate-all-around 1-D transistors MD Ganeriwala, C Yadav, FG Ruiz, EG Marin, YS Chauhan, ... IEEE Transactions on Electron Devices 64 (12), 4889-4896, 2017 | 13 | 2017 |
| Threshold voltage modeling of GaN based normally-off tri-gate transistor C Yadav, P Kushwaha, H Agarwal, YS Chauhan 2014 Annual IEEE India Conference (INDICON), 1-4, 2014 | 13 | 2014 |
Yogesh S. ChauhanFellow IEEE, FNAE, Professor-IIT KanpurVerified email at iitk.ac.in
