John Kalamatianos
John Kalamatianos
Fellow Design Engineer, AMD Research
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High-speed parallel-prefix module 2/sup n/-1 adders
L Kalampoukas, D Nikolos, C Efstathiou, HT Vergos, J Kalamatianos
IEEE Transactions on Computers 49 (7), 673-680, 2000
Method and apparatus for cache control
A Branover, NM Hack, MB Steinman, J Kalamatianos, JM Owen
US Patent 8,412,971, 2013
Area-time efficient modulo 2/sup n/-1 adder design
C Efstathiou, D Nikolos, J Kalamatianos
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1994
Lost in abstraction: Pitfalls of analyzing GPUs at the intermediate language level
A Gutierrez, BM Beckmann, A Dutu, J Gross, M LeBeane, J Kalamatianos, ...
2018 IEEE International Symposium on High Performance Computer Architecture …, 2018
Throttling computational units according to performance sensitivity
S Nussbaum, A Branover, J Kalamatianos
US Patent 8,443,209, 2013
Predicting indirect branches via data compression
J Kalamatianos, DR Kaeli
Proceedings. 31st Annual ACM/IEEE International Symposium on …, 1998
Temporal-based procedure reordering for improved instruction cache performance
J Kalamationos, DR Kaeli
Proceedings 1998 Fourth International Symposium on High-Performance Computer …, 1998
Detecting and correcting hard errors in a memory array
J Kalamatianos, JK John, R Gelinas, VK Sridharan, PE Nevius
US Patent 9,189,326, 2015
Altering performance of computational units heterogeneously according to performance sensitivity
S Nussbaum, A Branover, J Kalamatianos
US Patent 8,447,994, 2013
On characterizing near-threshold SRAM failures in FinFET technology
S Ganapathy, J Kalamatianos, K Kasprak, S Raasch
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
Compiler techniques to reduce the synchronization overhead of gpu redundant multithreading
M Gupta, D Lowell, J Kalamatianos, S Raasch, V Sridharan, D Tullsen, ...
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
Assessing the impact of hard faults in performance components of modern microprocessors
N Foutris, D Gizopoulos, J Kalamatianos, V Sridharan
2013 IEEE 31st International Conference on Computer Design (ICCD), 207-214, 2013
Analysis of temporal-based program behavior for improved instruction cache performance
J Kalamatianos, A Khalafi, DR Kaeli, W Meleis
IEEE Transactions on Computers 48 (2), 168-175, 1999
Distributed memory controller
MR Meswani, DA Roberts, Y Eckert, K Dev, J Kalamatianos, I Paul
US Patent App. 14/862,011, 2017
Assessing the effects of low voltage in branch prediction units
A Chatzidimitriou, G Papadimitriou, D Gizopoulos, S Ganapathy, ...
2019 IEEE International Symposium on Performance Analysis of Systems and …, 2019
Management of cache size
J Kalamatianos, EJ McLellan, P Keltcher, S Manne, RE Klass, ...
US Patent 9,021,207, 2015
Method and apparatus for using compression to improve performance of low voltage caches
J Kalamatianos, S Ganapathy, S Das, M Tomei
US Patent 10,884,940, 2021
Cache access arbitration for prefetch requests
R Jayaseelan, J Kalamatianos
US Patent 9,223,705, 2015
Stride prefetching across memory pages
J Kalamatianos, P Keltcher, M Evers, C Narasimhaiah
US Patent 10,671,535, 2020
Detecting multiple stride sequences for prefetching
J Kalamatianos, PE Keltcher
US Patent 9,304,919, 2016
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