Gabriel Caffarena
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A clustering approach to multireference alignment of single-particle projections in electron microscopy
COS Sorzano, JR Bilbao-Castro, Y Shkolnisky, M Alcorlo, R Melero, ...
Journal of structural biology 171 (2), 197-206, 2010
SQNR estimation of fixed-point DSP algorithms
G Caffarena, C Carreras, JA López, Á Fernández
EURASIP Journal on Advances in Signal Processing 2010, 2010
Fast and accurate computation of the round-off noise of linear time-invariant systems
JA López, G Caffarena, C Carreras, O Nieto-Taladriz
IET Circuits, Devices & Systems 2 (4), 393-408, 2008
Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits
G Caffarena, GA Constantinides, PYK Cheung, C Carreras, ...
IEEE Transactions on Circuits and Systems II: Express Briefs 53 (5), 339-343, 2006
FPGA acceleration for DNA sequence alignment
G Caffarena, C Pedreira, C Carreras, S Bojanic, O Nieto-Taladriz
Journal of Circuits, Systems, and Computers 16 (02), 245-266, 2007
Architectural Synthesis of Fixed‐Point DSP Datapaths Using FPGAs
G Caffarena, JA López, G Leyva, C Carreras, O Nieto-Taladriz
International Journal of Reconfigurable Computing 2009 (1), 703267, 2009
Fast and accurate power estimation of FPGA DSP components based on high-level switching activity models
R Jevtic, C Carreras, G Caffarena
International Journal of Electronics 95 (7), 653-668, 2008
High-level synthesis of multiple word-length DSP algorithms using heterogeneous-resource FPGAs
G Caffarena, JA Lopez, C Carreras, O Nieto-Taladriz
2006 International Conference on Field Programmable Logic and Applications, 1-4, 2006
Fast characterization of the noise bounds derived from coefficient and signal quantization
JA López, C Carreras, G Caffarena, O Nieto-Taladriz
Proceedings of the 2003 International Symposium on Circuits and Systems …, 2003
Tracking the pipelining-power rule along the FPGA technical literature
E Boemo, JP Oliver, G Caffarena
Proceedings of the 10th FPGAworld Conference, 1-5, 2013
A low-latency, low-power FPGA implementation of ECG signal characterization using hermite polynomials
MP Desai, G Caffarena, R Jevtic, DG Márquez, A Otero
Electronics 10 (19), 2324, 2021
Fixed-point refinement of ofdm-based adaptive equalizers: An heuristic approach
G Caffarena, A Fernández, C Carreras, O Nieto-Taladriz
2004 12th European Signal Processing Conference, 1353-1356, 2004
A formal method for optimal high-level casting of heterogeneous fixed-point adders and subtractors
R Sierra, C Carreras, G Caffarena, CAL Bario
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
FPGA for pseudorandom generator cryptanalysis
S Bojanić, G Caffarena, S Petrović, O Nieto-Taladriz
Microprocessors and Microsystems 30 (2), 63-71, 2006
A methodology for CFD acceleration through reconfigurable hardware
E Andrés, C Carreras, G Caffarena, MC Molina, O Nieto-Taladriz, ...
46th AIAA Aerospace Sciences Meeting and Exhibit, 481, 2008
Analysis of limit cycles by means of affine arithmetic computer-aided tests
JA López, G Caffarena, C Carreras, O Nieto-Taladriz
2004 12th European Signal Processing Conference, 991-994, 2004
Combined word-length allocation and high-level synthesis of digital signal processing circuits
G Caffarena
Ph. D. dissertation, Universidad Politécnica de Madrid, Madrid, Spain, 2008
Comparing scientific performance among equals
COS Sorzano, J Vargas, G Caffarena-Fernández, A Iriarte
Scientometrics 101, 1731-1745, 2014
Design and implementation of a hardware module for equalisation in a 4G MIMO receiver
AF Herrero, A Jimenez-Pacheco, G Caffarena, JC Quiros
2006 International Conference on Field Programmable Logic and Applications, 1-4, 2006
Hermite Polynomial Characterization of Heartbeats with Graphics Processing Units
A Gil, G Caffarena, DG Márquez, A Otero
International Work-Conference on Bioinformatics and Biomedical Engineering, 2014
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