Follow
Jaehyun Lee
Jaehyun Lee
Verified email at synopsys.com
Title
Cited by
Cited by
Year
Analysis of drain-induced barrier rising in short-channel negative-capacitance FETs and its applications
J Seo, J Lee, M Shin
IEEE Transactions on Electron Devices 64 (4), 1793-1798, 2017
1062017
Density functional theory based simulations of silicon nanowire field effect transistors
M Shin, WJ Jeong, J Lee
Journal of applied physics 119 (15), 2016
492016
Nano-electronic Simulation Software (NESS): a flexible nano-device simulation platform
S Berrada, H Carrillo-Nunez, J Lee, C Medina-Bailon, T Dutta, O Badami, ...
Journal of Computational Electronics 19, 1031-1046, 2020
292020
Simulation of the impact of ionized impurity scattering on the total mobility in Si nanowire transistors
T Sadi, C Medina-Bailon, M Nedjalkov, J Lee, O Badami, S Berrada, ...
Materials 12 (1), 124, 2019
232019
Investigation of Pt-salt-doped-standalone-multiwall carbon nanotubes for on-chip interconnect applications
J Liang, R Chen, R Ramos, J Lee, H Okuno, D Kalita, V Georgiev, ...
IEEE Transactions on Electron Devices 66 (5), 2346-2352, 2019
202019
NESS: new flexible nano-electronic simulation software
S Berrada, T Dutta, H Carrillo-Nunez, M Duan, F Adamu-Lema, J Lee, ...
2018 International Conference on Simulation of Semiconductor Processes and …, 2018
202018
Comprehensive study of cross-section dependent effective masses for silicon based gate-all-around transistors
O Badami, C Medina-Bailon, S Berrada, H Carrillo-Nunez, J Lee, ...
Applied Sciences 9 (9), 1895, 2019
192019
A worst-case analysis of trap-assisted tunneling leakage in DRAM using a machine learning approach
J Lee, P Asenov, M Aldegunde, SM Amoroso, AR Brown, V Moroz
IEEE Electron Device Letters 42 (2), 156-159, 2020
182020
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization
R Chen, L Chen, J Liang, Y Cheng, S Elloumi, J Lee, K Xu, VP Georgiev, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (4), 432-439, 2022
162022
Mobility of circular and elliptical Si nanowire transistors using a multi-subband 1D formalism
C Medina-Bailon, T Sadi, M Nedjalkov, H Carrillo-Nunez, J Lee, ...
IEEE Electron Device Letters 40 (10), 1571-1574, 2019
162019
Variability study of MWCNT local interconnects considering defects and contact resistances-Part I: pristine MWCNT
R Chen, J Liang, J Lee, VP Georgiev, R Ramos, H Okuno, D Kalita, ...
IEEE Transactions on Electron Devices, 2018
16*2018
Progress on carbon nanotube BEOL interconnects
B Uhlig, J Liang, J Lee, R Ramos, A Dhavamani, N Nagy, J Dijon, ...
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 937-942, 2018
162018
DTCO launches Moore’s law over the feature scaling wall
V Moroz, XW Lin, P Asenov, D Sherlekar, M Choi, L Sponton, LS Melvin, ...
2020 IEEE International Electron Devices Meeting (IEDM), 41.1. 1-41.1. 4, 2020
152020
p-Type Nanowire Schottky Barrier MOSFETs: Comparative Study of Ge-and Si-Channel Devices
W Choi, J Lee, M Shin
Electron Devices, IEEE Transactions on, 1-1, 2014
152014
Random dopant-induced variability in Si-InAs nanowire tunnel FETs: A quantum transport simulation study
H Carrillo-Nuñez, J Lee, S Berrada, C Medina-Bailón, F Adamu-Lema, ...
IEEE Electron Device Letters 39 (9), 1473-1476, 2018
142018
Understanding electromigration in Cu-CNT composite interconnects: A multiscale electrothermal simulation study
J Lee, S Berrada, F Adamu-Lema, N Nagy, VP Georgiev, T Sadi, J Liang, ...
IEEE Transactions on Electron Devices 65 (9), 3884-3892, 2018
132018
A physics-based investigation of Pt-salt doped carbon nanotubes for local interconnects
J Liang, R Ramos, J Dijon, H Okuno, D Kalita, D Renaud, J Lee, ...
2017 IEEE International Electron Devices Meeting (IEDM), 35.5. 1-35.5. 4, 2017
132017
Negative capacitance logic device, clock generator including the same and method of operating clock generator
MC Shin, JH Lee, DH Kang, JB Seo, WJ Jeong
US Patent 9,484,924, 2016
132016
Atomistic-to circuit-level modeling of doped SWCNT for on-chip interconnects
J Liang, J Lee, S Berrada, VP Georgiev, R Pandey, R Chen, A Asenov, ...
IEEE Transactions on Nanotechnology 17 (6), 1084-1088, 2018
112018
Quantum Enhancement of a S/D Tunneling Model in a 2D MS-EMC Nanodevice Simulator: NEGF Comparison and Impact of Effective Mass Variation
C Medina-Bailon, H Carrillo-Nunez, J Lee, C Sampedro, JL Padilla, ...
Micromachines 11 (2), 204, 2020
92020
The system can't perform the operation now. Try again later.
Articles 1–20