Analysis of drain-induced barrier rising in short-channel negative-capacitance FETs and its applications J Seo, J Lee, M Shin IEEE Transactions on Electron Devices 64 (4), 1793-1798, 2017 | 115 | 2017 |
Density functional theory based simulations of silicon nanowire field effect transistors M Shin, WJ Jeong, J Lee Journal of applied physics 119 (15), 2016 | 52 | 2016 |
Nano-electronic Simulation Software (NESS): a flexible nano-device simulation platform S Berrada, H Carrillo-Nunez, J Lee, C Medina-Bailon, T Dutta, O Badami, ... Journal of Computational Electronics 19, 1031-1046, 2020 | 34 | 2020 |
Carbon nanotube SRAM in 5-nm technology node design, optimization, and performance evaluation—part I: CNFET transistor optimization R Chen, L Chen, J Liang, Y Cheng, S Elloumi, J Lee, K Xu, VP Georgiev, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (4), 432-439, 2022 | 25 | 2022 |
Simulation of the impact of ionized impurity scattering on the total mobility in Si nanowire transistors T Sadi, C Medina-Bailon, M Nedjalkov, J Lee, O Badami, S Berrada, ... Materials 12 (1), 124, 2019 | 24 | 2019 |
DTCO launches Moore’s law over the feature scaling wall V Moroz, XW Lin, P Asenov, D Sherlekar, M Choi, L Sponton, LS Melvin, ... 2020 IEEE International Electron Devices Meeting (IEDM), 41.1. 1-41.1. 4, 2020 | 23 | 2020 |
A worst-case analysis of trap-assisted tunneling leakage in DRAM using a machine learning approach J Lee, P Asenov, M Aldegunde, SM Amoroso, AR Brown, V Moroz IEEE Electron Device Letters 42 (2), 156-159, 2020 | 21 | 2020 |
NESS: new flexible nano-electronic simulation software S Berrada, T Dutta, H Carrillo-Nunez, M Duan, F Adamu-Lema, J Lee, ... 2018 International Conference on Simulation of Semiconductor Processes and …, 2018 | 21 | 2018 |
Comprehensive study of cross-section dependent effective masses for silicon based gate-all-around transistors O Badami, C Medina-Bailon, S Berrada, H Carrillo-Nunez, J Lee, ... Applied Sciences 9 (9), 1895, 2019 | 20 | 2019 |
Mobility of circular and elliptical Si nanowire transistors using a multi-subband 1D formalism C Medina-Bailon, T Sadi, M Nedjalkov, H Carrillo-Nunez, J Lee, ... IEEE Electron Device Letters 40 (10), 1571-1574, 2019 | 17 | 2019 |
Investigation of Pt-salt-doped-standalone-multiwall carbon nanotubes for on-chip interconnect applications J Liang, R Chen, R Ramos, J Lee, H Okuno, D Kalita, V Georgiev, ... IEEE Transactions on Electron Devices 66 (5), 2346-2352, 2019 | 17 | 2019 |
Variability study of MWCNT local interconnects considering defects and contact resistances-Part I: pristine MWCNT R Chen, J Liang, J Lee, VP Georgiev, R Ramos, H Okuno, D Kalita, ... IEEE Transactions on Electron Devices, 2018 | 16* | 2018 |
Understanding electromigration in Cu-CNT composite interconnects: A multiscale electrothermal simulation study J Lee, S Berrada, F Adamu-Lema, N Nagy, VP Georgiev, T Sadi, J Liang, ... IEEE Transactions on Electron Devices 65 (9), 3884-3892, 2018 | 16 | 2018 |
Negative capacitance logic device, clock generator including the same and method of operating clock generator MC Shin, JH Lee, DH Kang, JB Seo, WJ Jeong US Patent 9,484,924, 2016 | 16 | 2016 |
p-Type Nanowire Schottky Barrier MOSFETs: Comparative Study of Ge-and Si-Channel Devices W Choi, J Lee, M Shin Electron Devices, IEEE Transactions on, 1-1, 2014 | 15 | 2014 |
Random dopant-induced variability in Si-InAs nanowire tunnel FETs: A quantum transport simulation study H Carrillo-Nuñez, J Lee, S Berrada, C Medina-Bailón, F Adamu-Lema, ... IEEE Electron Device Letters 39 (9), 1473-1476, 2018 | 14 | 2018 |
Progress on carbon nanotube BEOL interconnects B Uhlig, J Liang, J Lee, R Ramos, A Dhavamani, N Nagy, J Dijon, ... 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 937-942, 2018 | 13 | 2018 |
A physics-based investigation of Pt-salt doped carbon nanotubes for local interconnects J Liang, R Ramos, J Dijon, H Okuno, D Kalita, D Renaud, J Lee, ... 2017 IEEE International Electron Devices Meeting (IEDM), 35.5. 1-35.5. 4, 2017 | 12 | 2017 |
Heterogeneous integration enabled by the state-of-the-art 3DIC and CMOS technologies: Design, cost, and modeling XW Lin, V Moroz, X Xu, Y Gao, D Rennie, P Asenov, S Smidstrup, ... 2021 IEEE International Electron Devices Meeting (IEDM), 3.4. 1-3.4. 4, 2021 | 11 | 2021 |
Quantum Enhancement of a S/D Tunneling Model in a 2D MS-EMC Nanodevice Simulator: NEGF Comparison and Impact of Effective Mass Variation C Medina-Bailon, H Carrillo-Nunez, J Lee, C Sampedro, JL Padilla, ... Micromachines 11 (2), 204, 2020 | 9 | 2020 |